What is the pixel layout of a 1.14 inch IPS display?

The pixel layout of a 1.14 inch IPS display is typically a 240x135 resolution arrangement, which translates to a rectangular grid of 240 columns and 135 rows of individual pixels. This specific layout is common in small, round-cornered IPS screens used in wearables, smart home devices, and compact embedded systems. Each pixel is composed of three sub-pixels (red, green, and blue) in an RGB stripe configuration, which is standard for IPS technology to ensure consistent color reproduction and wide viewing angles. The pixel density for this size and resolution is approximately 240 pixels per inch (PPI), calculated by dividing the diagonal resolution (around 275 pixels, using the Pythagorean theorem: sqrt(240^2 + 135^2)) by the 1.14-inch diagonal. This high PPI makes text and icons appear sharp, even at close viewing distances, which is critical for applications like fitness trackers or smartwatches where screen real estate is limited.

The physical dimensions of the active area for a 1.14 inch 240x135 ips display are roughly 24.5 mm wide by 13.8 mm tall, with a pixel pitch of about 0.102 mm between adjacent pixels. This layout is optimized for SPI (Serial Peripheral Interface) communication, which uses a 4-wire interface (SCLK, MOSI, DC, CS) plus reset and backlight pins, allowing for efficient data transfer of 240x135 pixel frames at refresh rates up to 60 Hz. The 240x135 resolution is a non-standard aspect ratio of 16:9, but it’s slightly wider than typical 16:9 displays because the horizontal resolution is 240 pixels while vertical is 135 pixels, giving a ratio of 1.78:1. This is intentional for round-cornered displays, as the corners are cut off to match a circular or rounded bezel design, reducing the effective pixel count in the corners. The pixel layout is arranged in a landscape orientation by default, but the driver IC (like the ST7789 or similar) supports rotation via software commands, so you can flip the layout to portrait or inverted modes without changing the physical pixel grid.

From a technical standpoint, the 240x135 pixel layout is driven by a controller IC that supports 16-bit or 18-bit color depth, meaning each pixel can display up to 65,536 colors (16-bit) or 262,144 colors (18-bit). The pixel data is stored in a frame buffer inside the controller, which is 240 columns by 135 rows of memory cells. The controller uses a column-major ordering for data writes, so when you send pixel data over SPI, you typically start at column 0, row 0, and move horizontally across row 0, then down to row 1, and so on. This layout is efficient for displaying bitmap images because the memory mapping matches the physical pixel arrangement. The 240x135 resolution also has a specific window address mode, where you can define a rectangular region of pixels to update, reducing SPI traffic when only a portion of the screen changes—useful for partial updates in UI elements like battery icons or time displays.

The pixel layout’s density of 240 PPI is achieved through a combination of the display’s physical size and the driver IC’s ability to drive small pixels without crosstalk. The sub-pixel arrangement uses a standard RGB stripe, where each pixel is 0.102 mm wide and 0.102 mm tall, with the red, green, and blue sub-pixels stacked vertically in a single column. This is different from PenTile or other sub-pixel layouts that share sub-pixels between adjacent pixels, which can reduce effective resolution. The RGB stripe ensures that each pixel is fully independent, giving crisp edges for text and fine lines. The IPS (In-Plane Switching) technology further enhances the pixel layout by aligning liquid crystals in a plane parallel to the glass, which provides consistent color and brightness across the entire 240x135 grid, even at extreme viewing angles up to 85 degrees. This is a key advantage over TN (Twisted Nematic) displays, which often suffer from color shift and contrast loss when viewed off-axis.

Data from manufacturer spec sheets shows that the 1.14 inch IPS display has a typical contrast ratio of 1000:1, which is high for its size, and a brightness of 300-400 cd/m², depending on the backlight LED configuration. The pixel layout supports a 60 Hz refresh rate, but the SPI bus speed (typically up to 10 MHz for 3.3V logic) limits the actual frame rate. For a 240x135 display with 16-bit color, each frame requires 240 * 135 * 2 = 64,800 bytes of data. At 10 MHz SPI clock, the theoretical maximum frame rate is about 10,000,000 / (64,800 * 8) ≈ 19.3 frames per second, but with overhead for commands and delays, the practical rate is around 15-18 FPS. This is fine for static UI elements but not for video playback. Some displays use a 4-wire SPI with 8-bit or 9-bit command/data modes, which can slightly improve throughput by reducing command overhead. The pixel layout is also compatible with dithering techniques, where the controller can simulate more colors by alternating between two adjacent colors in a pattern, though this can reduce perceived sharpness.

The physical pixel layout is influenced by the display’s module design, which includes a glass substrate, polarizer, backlight, and flexible PCB (FPC) with a connector. The active area of 24.5 x 13.8 mm is surrounded by a bezel of about 1-2 mm on each side, making the total module size around 27.5 x 16.8 mm. The pixel grid is centered within this area, with the first pixel at coordinate (0,0) located at the top-left corner when viewed from the front. The backlight is typically a single white LED with a diffuser, and the brightness uniformity across the 240x135 grid is within 80% of the center value, as per typical IPS specs. The pixel layout also has a response time of 10-15 ms (gray-to-gray), which is fast enough for smooth animations in UI transitions, but not for gaming or high-speed motion.

For developers, the pixel layout is crucial for designing graphics. The 240x135 resolution means that a full-screen image must be 240 pixels wide and 135 pixels tall. If you’re using a font rendering library, you need to account for the pixel density: a 14-point font at 240 PPI will be about 14 * 240 / 72 = 46.7 pixels tall, which is large for this screen. So, you typically use smaller fonts like 8-10 points, which are 27-33 pixels tall, allowing for 4-5 lines of text. The pixel layout also supports partial updates, where you can update only a 10x10 pixel region for a cursor or icon, reducing SPI traffic and power consumption. The driver IC’s memory is organized as a 240x135 frame buffer, but you can also use it as a 240x240 buffer if you need to scroll content, by using the controller’s scroll mode, which shifts the displayed region vertically within a larger virtual buffer.

Here’s a table summarizing the key pixel layout parameters for a typical 1.14 inch IPS display:

Parameter	Value	Notes
Resolution	240 x 135 pixels	Landscape orientation by default
Pixel Density	~240 PPI	Based on 1.14-inch diagonal
Pixel Pitch	0.102 mm	Center-to-center distance
Active Area	24.5 x 13.8 mm	Width x height
Sub-pixel Layout	RGB stripe	Red, green, blue vertical columns
Color Depth	16-bit (65K colors) or 18-bit (262K colors)	Configurable via driver IC
Refresh Rate	60 Hz (max), 15-18 FPS practical	Limited by SPI bus speed
Interface	4-wire SPI	SCLK, MOSI, DC, CS, plus RST and BL
Driver IC	ST7789 or GC9A01	Common for 240x135 displays

The pixel layout also affects power consumption. Each pixel’s transistor and capacitor in the active matrix require a gate voltage to turn on, and the row drivers sequentially scan the 135 rows. The total power draw for the display panel alone is around 10-20 mW at typical brightness, but the backlight can consume 50-100 mW, depending on the LED current. The 240x135 layout means that the gate driver has to drive 135 lines, which is less than a 240x240 display, so the row scan time is shorter, reducing power slightly. The data driver (source driver) has to drive 240 columns, which is standard for small displays, and the RGB stripe layout means each column driver handles three sub-pixels, but the driver IC internally multiplexes the color data to the sub-pixels.

One common misconception is that the pixel layout is square, but it’s actually rectangular. The 240 horizontal pixels vs 135 vertical pixels means that if you display a perfect circle, it will appear slightly elliptical because the pixel aspect ratio is 1:1 (square pixels), but the overall shape is stretched horizontally due to the physical aspect ratio of the active area (24.5:13.8 ≈ 1.78:1). However, the pixels themselves are square, so the circle will be correctly proportioned if you consider the physical dimensions. This is important for drawing accurate shapes in software. The driver IC’s coordinate system maps (0,0) to the top-left pixel, and (239,134) to the bottom-right, with the pixel data being written in row-major order. Some controllers also support a “mirror” or “flip” mode that reverses the row or column order, which can be useful for mounting the display in different orientations.

For applications like a smartwatch, the pixel layout is often used with a circular mask, where the round corners of the display cut off the corners of the 240x135 grid. The actual visible pixels are those within a circle or rounded rectangle, so the effective pixel count is lower than 240x135. For example, a 1.14-inch round display might have a circular active area with a diameter of 1.14 inches, but the pixel grid is still 240x135, with the corners hidden by the bezel or a software mask. The pixel layout in the corners is still present, but they are not illuminated because the backlight diffuser or the glass cutout blocks them. This is a common trick to reduce cost by using a standard rectangular panel and then cutting the glass into a round shape.

Another angle is the compatibility with microcontrollers like ESP32, STM32, or Raspberry Pi Pico. The 240x135 pixel layout fits well within the memory constraints of these MCUs. For example, an ESP32 has 520 KB of SRAM, and a full frame buffer for 240x135 at 16-bit color requires 64.8 KB, which is about 12.5% of the total RAM. This leaves plenty of room for the application code and other data. The SPI interface for this layout typically uses a 3.3V logic level, and the pixel data is sent as 16-bit words (two bytes per pixel), with the MSB first. The driver IC expects the data in RGB565 format, where bits 15-11 are red, 10-5 are green, and 4-0 are blue. So, the pixel layout directly influences the data format you need to use in your code.

In terms of manufacturing, the pixel layout of a 1.14 inch IPS display is produced using a photolithography process that patterns the thin-film transistors (TFTs) and pixel electrodes on the glass. The 240x135 grid requires 240 data lines and 135 gate lines, which are routed to the driver IC via a flexible printed circuit. The pixel pitch of 0.102 mm is achievable with standard 2-3 micron lithography, which is common for small displays. The RGB stripe sub-pixels are created by depositing red, green, and blue color filters on the color filter glass, aligned with the TFT array. The IPS technology uses a common electrode on the bottom glass and a pixel electrode on the top glass, with the liquid crystal molecules aligned in a plane, which gives the wide viewing angle. The pixel layout’s uniformity is checked during manufacturing by testing the brightness and color of each pixel, with a typical defect rate of less than 10 ppm (parts per million) for dead pixels.

To give you a concrete example, the 1.14 inch IPS display from DisplayModule (model 1.14 inch 240x135 IPS display) uses a GC9A01 driver IC, which supports 240x135 resolution with 16-bit color. The pixel layout is exactly as described: 240 columns, 135 rows, RGB stripe, 0.102 mm pitch, 24.5 x 13.8 mm active area. The module includes a 0.5 mm thick glass, a 0.3 mm polarizer, and a 0.6 mm backlight, making the total thickness about 1.4 mm. The FPC has a 1.0 mm pitch connector with 8 pins, including power, ground, SPI, and backlight control. The pixel layout is optimized for low power, with a typical current draw of 15 mA for the panel and 25 mA for the backlight at 3.3V, giving a total power of about 132 mW. This is suitable for battery-powered devices like a fitness tracker, where the display is updated only a few times per second.

If you’re designing a PCB for this display, the pixel layout affects the trace routing. The SPI lines should be kept short (less than 10 cm) to avoid signal integrity issues at 10 MHz. The pixel data is sent in bursts, and the controller’s internal frame buffer allows you to update the entire screen or just a window. The window address mode uses four registers: column start, column end, row start, and row end, which define a rectangular region of the 240x135 grid. For example, if you want to update only the top left 100x50 pixel area, you set the column range from 0 to 99 and the row range from 0 to 49, then send only 100 * 50 = 5000 pixels of data. This is much faster than updating the entire 32,400 pixels, and it’s a key feature of the pixel layout for efficient UI updates.

Finally, the pixel layout’s compatibility with existing libraries like Adafruit GFX or TFT_eSPI is straightforward. These libraries treat the display as a 240x135 canvas, with functions like drawPixel(x, y, color) that map directly to the pixel grid. The coordinate system is (0,0) at top-left, and (239,134) at bottom-right. The libraries also handle the color conversion to RGB565 automatically. The pixel layout supports rotation, so you can display content in landscape, portrait, or inverted orientations by setting the MADCTL register in the driver IC. This changes the column and row mapping, but the physical pixel grid remains the same. So, whether you’re building a simple clock or a complex UI, the 240x135 pixel layout gives you a solid foundation for crisp